1. Technical Field
This invention relates generally to hardware interruptions, such as processor interruptions, and more particularly to the handling of such interruptions by an operating system, as called by an interruption handler for such handling.
2. Description of the Prior Art
The processors of modern computer systems typically have the ability to generate interruptions. Interruptions can be generally defined as events that occur during processing of instructions by the processor. In one type of processor architecture, the Intel Architecture-64 (IA-64), which includes ITANIUM processors manufactured by Intel Corp., of Santa Clara, Calif., there are four different types of interruptions. These types are aborts, interrupts, faults, and traps.
Aborts occur when the processor has detected an internal malfunction, referred to as a machine check (MCA), or a processor reset (RESET). The abort may cause the processor to suspend the instruction stream at an unpredictable location, with partially updated register or memory state. Interrupts are generated by an external or independent entity, such as an input/output (I/O) device, a timer event, or another processor. Faults result from processor instructions that request actions that cannot or should not be carried out, or when system intervention is required before an instruction is executed. Somewhat similarly, traps result from processor instructions in which system intervention is required immediately after an execution is executed.
Interruptions can be handled within the processor itself, by system firmware, or by an operating system executed by the processor. In the IA-64 processor architecture, interruption vector address (IVA)-based interruptions are serviced by the operating system, whereas processor abstraction layer (PAL)-based interruptions are serviced by the firmware of the processor or the operating system. In this architecture, all aborts and some interrupts are PAL-based interruptions. All faults and traps, and some interrupts, are IVA-based interruptions.
For machine check aborts in particular, the processor transfers execution to a processor error handler in the PAL, which itself transfers execution to a platform error handler in a system abstraction layer (SAL) of the architecture. The platform error handler, also referred to as a machine check handler (MCH), in turn transfers execution to the operating system's MCH, at a predetermined handling point in the operating system. The operating system's MCH ultimately returns execution to the platform error handler.
However, operating system responsibility for handling machine check aborts can be problematic. Each operating system that may run on the processor architecture must have the necessary intelligence to interpret the machine check aborts in the context of the system hardware implementation, and determine an appropriate course of action as to remedying the problem. The processor architecture itself typically only passes the abort to the operating system, usually without providing any further information regarding the machine check.
This means that for a number of different operating systems that may run on the processor architecture, duplication of effort is required so that each operating system is able to properly handle machine check aborts and other interruptions. The common entity in such different computer systems, the processor architecture, only passes the machine checks to the currently running operating system, without providing any further information regarding the aborts or recommendation as to course of action for handing the aborts. For these described reasons, as well as other reasons, there is a need for the present invention.